One stack, two timelines.

Planned stack

The layers below describe the architecture under development. Released components will be listed on the publications page with their benchmarks.

Application APIs

Domain SDKs (sensing, finance, biology, optimisation) on top of a unified hybrid runtime.

Hybrid Runtime

Scheduler that routes circuits between classical accelerators, simulators, and quantum backends.

Compiler

Topology aware transpilation, noise aware mapping, and qubit reuse across multiple backends.

Simulators

State vector, tensor network, and stabilizer simulators with mixed precision GPU paths.

Noise & Error Models

Calibrated device models, mid circuit measurement, and lightweight QEC primitives.

Sensing Toolchain

Signal chain modelling for atomic clocks, magnetometers, and entangled photonics.

Materials Pipelines

First principles, tensor network, and ML potentials for quantum hardware design.

Design principles

Named baselines. Each benchmark we publish will name the backend, the noise model and the classical baseline.

Composable. Each layer of the stack is designed to be usable on its own: the compiler without our runtime, the simulators without our SDK.

Reproducible. Each release will include container images, fixed random seeds and a script that reproduces its results.

Indian by design. The stack is being designed around Indian device topologies, fabrication constraints and regulatory contexts.

What we are not

We are not a hardware company. We do not fabricate qubits or build dilution refrigerators. We are building the software, simulation and tooling layer that helps Indian quantum hardware become useful as it becomes available.